Special Subject Book January 2000 Thermal Resistance Theory and Practice http://www.infineon.com SMD Packages Never stop thinking Edition January 2000 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen (c) Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Thermal Resistance - Theory and Practice Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SMD-Package Properties for Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Using a Printed Circuit Board as a Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Static Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Dynamic Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Finite Element Method (FEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Determining the Static Heat Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Measuring the Rthj-a in the Real Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Determining the Dynamic Heat Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package and Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Infineon Technologies AG 3 Thermal Resistance - Theory and Practice Introduction Power-SMD applications or what's the size of the heat sink ? More and more frequently, modern SMD-component users (Surface Mounted Devices) ask the question, "What's the size of the heat sink ?" The reason: The trend from through-hole packages to low-cost SMD-applications is marked by the improvement of chip technologies. Silicon instead of heat sink" is therefore possible in many cases. The printed circuit board (PCB) itself becomes the heat sink. As many applications today use PCBs assembled with SMDtechnology, the emphasis is on Power-ICs in SMD packages mounted on single-sided PCBs laminated on one side. Pricing pressure demands simple processes and lowest-cost solutions. This report describes a solution. 4 Infineon Technologies AG SMD-Package Properties for Power Applications packages. Metal bridges are connected between the chip carrier (lead frame) and the pins. From the outside, this package looks identical to standard components because the plastic molding compound conceals these details. Figure 1 shows both types of packages with the examples P-TO252-3-1 (D-Pack) and P-DSO-14-4 (3 center pins each per side of the cooling path). The internal structure is described in more detail in this report and can be seen in Figure 11. There are two basic groups of packages: Heat Sink packages are the first group.The heat sink (chip carrier lead frame) is soldered directly to the PCB. The thermal resistance of this packages between chip and heat sink is called Rthj-c (junction-case) and has low values. Thermal Enhanced Leadframes constitute the second group of Footprint / Dimensions 5.8 Package e A L B P-DSO-14-4 1.27 5.69 1.31 0.65 e 2.2 10.6 6.4 L B 1.2 5.76 0.35 x 45 4 -0.2 1) 0.51 min 1.27 0...0.15 0.5 +0.08 -0.04 3x 0.75 0.1 2.28 0.25 0.1 0.35 +0.15 2) 0.4 +0.8 0.2 14x 6 14 8 max. 0.2 -0.1 1.45 -0.2 0.8 0.15 1 0.1 (4.17) 9.9 0.5 6.22 -0.2 4.57 0.9 +0.08 -0.04 B 5.4 0.1 1.75 max. 2.3 +0.05 -0.10 A 0.15 max per side A 0.19 +0.06 +0.15 6.5 -0.10 0.2 8 10.1 M A B All metal surfaces thin plated, except area of cut. 1 7 8.75 -0.21) 0.1 Index Marking P-TO252-3-1 P-DSO-14-4 Dimensions in mm Figure 1 Heat Sink - vs. Thermal Enhanced Package Types Infineon Technologies AG 5 Thermal Resistance - Theory and Practice Using a printed circuit board as a heat sink ? How do I calculate that ? How big does my heat sink need to be ? Which size do we need ? In earlier fabrications, a solid heat sink was either screwed or clamped to the power package. It was easy to calculate the thermal resistance from the geometry of the heat sink. In SMD-technology, this calculation is much more difficult because the heat path must be evaluated: chip (junction) - lead frame - case or pin - footprint PCB materials (basic material, thickness of the laminate) - PCB volume - surroundings. As the layout of the PCB is a main contributor to the result, a new technique must be applied. The Appendix proivdes thermal data for all packages listed in Table 1. Let us start with some theoretical considerations: Static Properties To facilitate discussion of the static properties of a Power IC (PIC), the internal structure of a PIC and its method of mounting on a PCB or heat sink is illustrated in Figure 2. The PIC consists of a chip mounted on a chip carrier or lead frame, and held by solder or bonding adhesive. The lead frame consists of a high-conductivity material such as copper, and can have a 6 Infineon Technologies AG Package Heat Sink / Pin P-DSO-8-1 - P-DSO-14-4 Pin 3-5; 10-12 P-DSO-16-1 - P-DSO-20-1 - P-DSO-20-6 Pin 4-7; 14-17 P-DSO-24-3 Pin 5-8; 17-20 P-DSO-28-6 Pin 6-9; 20-23 P-DSO-20-10 Tab P-DSO-36-10 Tab SCT-595-5-1 Pin 2; 5 SOT-223-4-2 Tab or Pin 4 P-TO252-3-1 (D-Pack) Tab P-TO263-5-1 Tab Table 1 The Most Important SMD-Packages thickness of several millimeters. The associated static equivalent circuit is shown in Figure 3. The following analogies with electrical quantities have been used: Molding compound (Molding) C The power dissipation PV occurring close to the chip surface is symbolized by a current source. Chip (Die) Chip adhesive / Lot (Die bond) Chip carrier (Leadframe) Solder C The thermal resistances are represented by ohmic resistors. The "resistance" network is essentially a serial connection to the ambient temperature. As a first approximation, the parallelconnected thermal resistance of the molding (broken lines) can be neglected in power packages. Heat sink or PCB (Heat sink) Figure 2 Internal Structure of a PIC and Method of Mounting on a Heat Sink C The ambient temperature is represented by a voltage source. In accordance with the analogy, the thermal current PV = Q/t can now be calculated from the "thermic Ohm's law" V = I * R as Tj - Ta = PV * Rthj-a. Rth Molding PV Tj Rth Rth Rth Rth Rth Die Die bond Leadframe Solder Heat sink Tc Rthj-c Rth Application = Ta For the purpose of discussing the application as a whole, the function PV = (Ta) is of practical interest. One obtains: PV = - Ta / Rthj-a + Tj / Rthj-a. This is a descending straight line of gradient -1 / Rthj-a with its zero at Tj. Rthj-a Figure 3 Static Equivalent Circuit for the Structure shown in Figure 2 Infineon Technologies AG 7 Thermal Resistance - Theory and Practice In Figure 4, this function is shown for the P-DSO-14-4 Package (Thermal Enhanced Power Package) mounted on the standard application board. From this function, the user can derive the permissible power dissipation directly for any ambient temperature. At Ta = 85 C, for example, the permissible dissipation is approxi-mately 0.7 W. The exact value can be calculated from the equation PV = (Tj - Tamax) / Rthj-a = 65 K / 92 K/W = 0.7 W. It should be noted that in the data sheets of the PICs the power dissipation is given as a function of the package (case) temperature TC, because the applicationspecific thermal resistances are not known to the manufacturer. This function, like the previous one, is a descending straight line. The slope now has the value 1 / Rthj-c. The zero remains at Tj. As an example, this function is presented in Figure 5 for the P-TO252-3-1 Package. The new P-TO252-3-1 package has a thermal resistance of max. 4 K/W and is unique in the small size of its base area when compared with packages of equivalent performance (PCB board area). At approximately 30 C, the permissible power dissipation is 30 W. Higher power dissipation is prevented by intervention of the chip-internal current limiters. For this reason, the value for power dissipation at lower temperatures remains constant. 8 Infineon Technologies AG PV W PVO = 1.63 1.08 Tj Rthj-a = 150 W 1.63 W 92 Parameter: Tjmax = 150 C Rthj-a = 92 K/W Tamax = 85 C PV = 1 W T = 92 C 0.54 Tamax 0 0 50 100 Tj Ta 150 C Figure 4 Permissible Power Dissipation of the P-DSO-14-4 Package Mounted on a PCB with 300 mm Cooling Area, as a Function of Ambient Temperature PV W 30 Rthj-c = 4 K/W 20 10 0 0 50 100 Figure 5 Permissible Power Dissipation of the P-TO252-3-1 as a Function of the Package (Case) Temperature 150 C TC Dynamic Properties As mentioned earlier, the thermal behavior of PICs changes when dynamic phenomena are considered (pulse power operation). This behavior can be described in terms of thermal capacity Cth, which is directly proportional to the relevant volume V (in cm), to the density (in g/cm) of the material and to a proportionality factor of the specific heat c in Ws/g * K. The applicable equation is: Cth = c * * V = m * c This means: The thermal capacity of a body of mass m = * V corresponds to the quantity of heat needed to heat the body by 1 C. To calculate the temperature change T it is necessary to use the quantity-of-charge equation for a capacitance C. The equation is: V*C=I*t=Q By analogy, the quantity-of-heat equation is: T * Cth = P * t = Q This means: Just as the current I = Q/t represents a transport of charge per unit of time, the power dissipation P represents the transport of thermal energy per unit of time. Consequently: T = P * t Cth Die PV CthD 3 mWs/K D = 1.5 ms The equivalent circuit of the P-TO263-7-3 power package, with the thermal capacities added, is shown in Figure 6. The thermal capacities calculated from the material and the volume are shown in parallel with the thermal resistances. When calculating the components of a network it is necessary to know the thickness d, the crosssectional area A and the thermal conductivity L in W/m * K, in order to obtain the appropriate thermal resistance Rth. The formula is: Rth = d L*A K W [] Heat sink RthD RthHS 0.48 K/W 0.24 K/W CthHS 300 mWs/K = Tcase HS = 70 ms Figure 6 Thermal Equivalent Circuit of the P-TO263-7-3 Package (Simplified) Infineon Technologies AG 9 Thermal Resistance - Theory and Practice 4.7 0.5 1.3 0.3 8 1) 6x1.27 9.4 0.8 10.8 2.4 2.7 0.3 1 0.3 7x0.6 0.1 0.05 B A 9.25 0.2 (15) 1.270.1 0.1 8.5 1) Footprint 0.47 9.8 0.15 8.42 4.4 10 0.2 4.6 16.15 0...0.15 0.5 0.1 0.25 M 0.1 1) Typical All metal surfaces tin plated, except area of cut. A B 8 max. Figure 7 Outline Drawing of the P-TO263-7-3 Power Package To calculate the thermal capacity Cth, it is necessary to know the volume V = d * A, the specific weight in g/cm3 and the specific thermal capacity c in Ws/g * K. The thermal capacity Cth is calculated from: Cth = m * c (Ws/T). The package dimensions are shown in Figure 7. Parameters for the Chip Symbol Value Dimension Area Thickness Thermal conductivity of silicon Thermal resistance of chip Specific weight of silicon Mass of chip Spec, thermal capacity of Si Thermal capacity of chip Thermal time constant of chip AD dD LSi RthD Si mD cSi CthD D 5 360 150 0.48 2.33 4.2 approx. 0.7 approx. 3 approx. 1.5 mm m W/m * K K/W g/cm mg Ws/g * K mWs/K ms Parameters for the Heat Slug Symbol Value Dimension Area (effective area of 64 mm) Thickness Thermal conductivity of cooper Thermal resistance of heat slug Specific weight of cooper Mass of heat slug Spec, thermal capacity of Cu Thermal capacity of heat slug Thermal time constant of heat slug AHS dHS LCu RthHS Cu mHS cCu CthHS HS 14 1.27 384 0.24 8.93 0.8 0.385 310 70 mm mm W/m * K K/W g/cm g Ws/g * K mWs/K ms Table 2 Parametric Data of the P-TO263-7-3 10 Table 2 lists all the important parametric data of the P-TO263-7-3 package. Infineon Technologies AG The die bond and molding components have been omitted from this discussion because they do not significantly influence the calculation of Rthj-c. For reference, these data are listed here: The time constance of the die bond is smaller than that of the chip by two orders of magnitude and can, thus, be neglected. The thermal resistance RthM of the molding is even three orders of magnitude bigger than that of the chip and that of the heat slug, and, being in parallel, can be neglected also. Pulse operation and the associated chip temperature responses also deserve examination. In accordance with the analogy to electrical systems, the chip temperature response can be viewed like a voltage increase across an C RthDB = 0.01 to 0.1 K/W; C CthDB = 0.1 to 0.5 mWs/K; C DB = 1 to 50 ms; C RthM = 100 K/W; C CthM = 0.64 Ws/K and C M = 64 s. (Die Bond = index: DB; molding = index: M) PV RC section which is being fed by a current pulse generator. The following relationship applies: V(t) = R * I * (1 - et/R C) and for the increase in temperature: T(t) = Rth * P * (1 - et/R C ) * th * th This heating-up and cooling-down process is presented qualitatively in Figure 8 (valid for tp >> 2 ms only). The chip temperature goes up and down between Tmin and Tmax. The variation depends on the magnitude of the power pulse and its duty cycle. T t tp Tj Tmax Tavg Tmin t Figure 8 Chip Temperature Tj vs. Time, for Periodic Pulse Operation Infineon Technologies AG 11 Thermal Resistance - Theory and Practice This junction temperature transients can be represented in the form of a function if the dynamic thermal impedance Zth = (Tmax - Tmin) / PV is shown versus pulse width tp for different duty cycles (duty cycle = DC = tp/T) (Figure 9). A special case of this representation is the dynamic thermal impedance in single-pulse operation (DC = 0). Figure 10 shows the thermal impedance in single-pulse operation for the medium-power package P-DSO-14-4 for three different cooling areas on the PCB. This function clearly shows the regions of dominance of the various time constants of the chip, the lead frame, and the PCB. The chip time constant tD lies in the millisecond range, whereas the lead frame dominates in the range of several 100 ms and the PCB in the 100-second range. 10 0 120 K/W K/W Footprint Zthj-a Zthj-c 100 10 -1 80 10 -2 10 -3 D= 0.50 0.20 0.10 0.05 0.02 0.01 single pulse 300 mm 2 60 600 mm 2 40 20 10 -4 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 s 10 0 tp Figure 9 Dynamic Thermal Impedance Zthj-c of a P-TO263-7-3 Package 12 Infineon Technologies AG 0 -3 10 -2 10 10-1 100 101 102 s 103 tp Figure 10 Thermal Impedance of the P-DSO-14-4 Package for Single-Pulse Operation Finite Element Method (FEM) The steps of the Finite Element Method (FEM) are explained below and one example is provided per group. P-TO252-3-1 The geometric data of the package is entered into the FEM model to calculate the thermal resistance. This avoids timeconsuming measurements. Figure 11 shows an implemented model. P-DSO-14-4 Figure 11 FEM Model of Heat Sink and Thermal Enhanced Package Infineon Technologies AG 13 Thermal Resistance - Theory and Practice The temperatures of the individual components (chip, diepad, molding compound, and leadframe) can be viewed individually or in combination (Figure 12). Chip with two active areas (dice only) Mold compound without cooling tab,chip and lead frame P-TO252-3-1 without mold compound with PV = 3 W for determining the Rthj-c Chip and lead frame of the SOT223-4-2 package on a PCB with heat sink Lead frame of the SCT595-5-1 on a PCB with heat sink SOT223-4-2 on a PCB with 6 cm heat sink; Rthj-a ~ 70 K/W is calculated at PV = 0.5 W Figure 12 FEM Analysis Possibilities 14 Infineon Technologies AG Three different PCBs have been created for each package model. They differ in the size of the copper laminated area A (heat sink) which is linked to the heat dissipating parts of the case (diepad in the P-TO252-3-1 or center pins in the P-DSO-14) (Figure 13). P-DSO-14-4 2 3 cm 0.375 a/2 P-DSO-14-4 -16-1 3 Footprint only 0.375 a/2 a a 0.67 1 6 cm P-DSO-14-4 1 1 1 Application-Board for Rth Measurement Rth-P-DSO-14-4 LP 1.0 P-TO252-3-1 P-TO252-3-1 a 1 6 cm I 1 3 2 3 cm a/2 P-TO252-3-1 a Footprint only a/2 I Q Q 1 I Q 1 Application-Board for Rth Measurement Rth-P-TO252-3-1 LP 1.1 Figure 13 PCB-Layout for FEM-Simulation P-DSO-14-4 and P-TO252-3-1 Infineon Technologies AG 15 Thermal Resistance - Theory and Practice Determining the Static Heat Resistance value depends only slightly on the active chip area. It is sufficient to simulate just one medium-sized chip (>2 mm). If the static thermal resistance Rthj-a is applied versus the PCB heat sink area, a very important function is obtained for the application of the component. By estimating the heat sink area in a real application, the user can The FEM simulation calculates the thermal static resistance Rthj-a (junction-ambient) and the Rthj-c (junction-case) for packages with enhanced die-pad or Rthj-pin (junction to a defined pin) for thermal enhanced P-DSO packages without die-pad. This easily determine the expected Rthj-a, especially as the simulated values are calculated in still air. Therefore, they represent the "worst case". In real applications the values for the heat resistance are much lower. At an air stream of 500 lin ft/min (linear feet per minute) the Rthj-a of the P-DSO-14-4 for example is up to 15 % lower (Figure 15). P-DSO-14-4 Rthj-a 120 K/W 112 P-TO252-3-1 Rthj-pin = 31.7 K/W Rthj-a 160 K/W 143.9 Rthj-c = 1.8 K/W 100 92 90 120 80 78 70 100 80 78 60 60 50 40 54.7 0 100 200 300 400 500 mm 2 600 40 0 100 200 300 500 mm 2 600 400 A A Figure 14 Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A at zero airflow P-DSO-14-4 P-TO252-3-1 120 K/W Rthj-a 110 160 K/W Rthj-a 140 Footprint only A = 300 mm 2 A = 600 mm 2 100 120 90 100 80 80 70 60 60 0 100 200 300 400 m/min 600 40 Footprint only A = 300 mm 2 A = 600 mm 2 0 Airspeed Figure 15 Thermal Resistance Junction to Ambient Rthj-a vs. Airspeed for the P-DSO-14-4 and P-TO252-3-1 Packages 16 Infineon Technologies AG 50 100 150 Airspeed m/min 200 Measuring the Rthj-a in a Real Application: To measure the chip temperature (Tj) requires a little trick: A temperature sensor is required on the chip which can also be read during operation. In many products a substrate diode can be used at an output (Status, Reset, etc.) to measure the chip temperature. To do this, the forward voltage VF of the diode is measured at load independent current as a calibration curve. Due to the characteristic temperature behavior of the forward voltage - it has a negative temperature coefficient of approx. -2 mV/K - the relevant chip temperature can be determined. Using the measurement described below the real thermal resistance can be determined. To determine the actual Rthj-a the temperature difference between chip temperature Tj and ambient temperature Ta is required. The equation Rthj-a = Tj - Ta applies. PV The power loss PV and the ambient temperature Ta can be determined easily in a temperature chamber or calculated. The calibration curve is measured in the temperature chamber with airflow. The power loss should be kept as low as possible to ensure the chip temperature remains equal to the ambient temperature. For the voltage regulator TLE 4269 GM (P-DSO-14-4 Package) a calibration curve (measured at the diode at the reset output, pin 7). RO is illustrated in Figure 16. Figure 17 shows the corresponding measuring circuit. 700 mV VF 600 500 400 300 200 100 0 0 50 100 C 150 T Figure 16 Calibration Curve TLE 4269 GM for IRO = -500 A (current drawn from Pin 7; RO) Infineon Technologies AG 17 Thermal Resistance - Theory and Practice The Rthj-a of any application can be determined by measuring the forward voltage of an output with substrate diode during operation (Figure 17). When the switch S1 is closed and the output voltage VQ = 5 V, the output current is 5 A. 35 The power loss PV = (VI - VQ) * IQ forward voltage VF of the diode. The appropriate Tj for every VF value can be read from the calibration curve VF = (Tj). The exact heat resistance of the real application is calculated with this values in the formula Rthj-a = in the chip of the voltage regulator is now 1 W. Now, change the ambient temperature Ta and measure the respective Tj - Ta PV Parameters such as air flow can be changed without affecting the measuring accuracy. TLE 4269 GM I TPower 13 9 Q RPU 20 k VI = 12 V CI 10 F Substrat diode of TRO P-DSO-14-4 1. Measurement of function VF = f (Ta): S1 open; we get IQ = 0 mA and PV = VI * II ~ 0 mW Ta ~ Tj Figure 17 Measuring Circuit with TLE 4269GM 18 Infineon Technologies AG 7 RO TRO 3-5; 10-12 IF ~ 500 A RF RL 100 k VF ~ 0.7 V VB 50 V 35 - + 2. Measurement of thermal resistance junction to ambient Rthj-a: S1 closed; we get IQ = VQ / RQ and PV = (VI - VQ) * IQ ~ 1 W Tj then can be found by measuring VF at given Ta from function VF vs. Ta then we get Rthj-a = (Ta - Tj) / 1 W S1 CQ 22 F PV = Power losses Ta = Ambient temperature Tj = Junction temperature Determining the Dynamic Heat Resistance The FEM analysis is used also for dynamic processes. As described above, the dynamic thermal impedance is defined as the ratio of the temperature difference T = Tj - Ta (chip temperature - start temperature) after the time tp to the power loss. If a transient FEM simulation is performed, it is easy to obtain the graph Zthj-a = (tp) (dynamic thermal impedance as a function of the pulse width tp). For the P-TO252-3-1 (D-Pack) and the P-DSO-14-4 the thermal impedances for the abovementioned PCB configurations are specified (Figure 18). The peak temperatures can be calculated easily from these curves: - - - - - P-TO252-3-1 (D-Pack) 3 cm heat sink Power loss PV = 10 W Pulse width tp = 200 ms Ambient temperature Ta = 85 C. From the middle curve (Figure 18), the Zthj-a of approximately 3.5 K/W at tp = 200 ms gives a temperature rise T = PV x Zthj-a of 35 K and finally a peak temperature Tjmax of 85 C+35 C = 120 C. P-DSO-14-4 P-TO252-3-1 120 K/W Zthj-a 100 Zthj-a 120 Footprint 300 mm 2 600 mm 2 80 160 K/W 100 60 80 Footprint 300 mm 2 600 mm 2 60 40 40 20 0 -3 10 20 10-2 10-1 100 101 102 tp s 103 0 -3 10 10-2 10-1 100 101 102 tp s 103 Figure 18 Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp Infineon Technologies AG 19 Thermal Resistance - Theory and Practice Summary For each case listed in Table 1, a Package and Thermal Information" data sheet is provided in the appendix.Each data sheet shows the footprint and case dimensions. The various versions of the PCBs used for the simulation are shown. It shows the heat distribution diagrams and the result diagrams of the FEM simulation. The left side shows the diagram of the static thermal resistance Rthj-a depending on the PCB heat sink area A. It includes the related thermal resistance Rthj-c (junction-case) or Rthj-pin. 20 Infineon Technologies AG On the right side is the diagram for the dynamic heat resistance Zthj-a, with three graphs for the various PCB heat sinks depending on the single pulse duration tp. This information is a valuable aid for SMD Power applications. It is intentionally limited to PCBs laminated on one side because it represents the cost optimum. For double sided PCBs or multilayers a simple attempt with conductance cross sections can be made to determine the change in the PCB thermal resistance (compare thermal data sheet of P-DSO-20-10 with P-DSO-36-10 in the appendix). The PCBs are usually installed in closed plastic cases. The most favorable heat path then usually forms at plug contacts to the cables because a supply wire with an adequate cross section is ideal as a heat conductor. The future of chip placement requires mechatronic solutions where the PCB can be replaced by chip-connector-supply wire configurations. Package and Thermal Information Appendix P-DSO-8-1 22 P-DSO-14-4 23 P-DSO-16-1 24 P-DSO-20-1 25 P-DSO-20-6 26 P-DSO-24-3 27 P-DSO-28-6 28 P-DSO-20-10 29 P-DSO-36-10 30 SCT595-5-1 31 SOT223-4-2 32 P-TO252-3-1 33 P-TO263-5-1 34 Infineon Technologies AG 21 P-DSO-8-1 1.27 L 8 max. 0.4 +0.8 6 0.2 0.1 0.35 +0.15 2) 0.2 8x 8 5 B e 4 -0.21) 0.19 +0.06 e A L B 1.27 5.69 1.31 0.65 0.35 x 45 1.75 max. Package P-DSO-8-1 0.2 -0.1 1.45 -0.2 Footprint/Dimensions A 1 4 5 -0.21) Reflow soldering Index Marking PC-Board Dimensions in mm Application-Boards for Rth - Measurement P-DSO-8-1 P-DSO-8-1 a/2 2 3 cm 3 Footprint only a/2 0.375 0.67 0.67 0.375 a a 1 6 cm P-DSO-8-1 1 1 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 17.32 mm Finite Element Method FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 12.247 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 0.5 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 369 K A = 300 mm; Ta = 298 K; Tmax = 380 K Footprint only; Ta = 298 K; Tmax = 390 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) 190 K/W 185 Rthj-a Rthj-pin2 = 71.8 K/W 170 Zthj-a 164 160 150 140 142 130 120 110 100 0 100 200 300 400 500 mm 2 600 A 22 22 Infineon Technologies AG Infineon Technologies AG 200 K/W Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) 160 140 120 100 80 60 40 20 0 -3 10 Footprint 300 mm 2 600 mm 2 10-2 10-1 100 101 102 tp s 103 Package and Thermal Information P-DSO-14-4 8 max. 4 -0.2 1) 0.19 +0.06 Package e A L B P-DSO-14-4 1.27 5.69 1.31 0.65 0.35 x 45 1.75 max. 0.2 -0.1 1.45 -0.2 Footprint/Dimensions 1.27 L 0.1 0.35 +0.15 2) 0.4 +0.8 0.2 14x GND 6 0.2 GND 8 B e 14 A 1 7 8.75 -0.21) Reflow soldering Index Marking Dimensions in mm Application-Boards for Rth - Measurement P-DSO-14-4 1 6 cm PC-Board P-DSO-14-4 2 3 cm 0.375 a/2 P-DSO-14-4 -16-1 3 Footprint only 0.375 a a 0.67 a/2 1 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 17.32 mm 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 12.247 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) A = 600 mm; Ta = 298.1 K; Tmax = 377.7 K A = 300 mm; Ta = 298 K; Tmax = 389.8 K Finite Element Method Footprint only; Ta = 298 K; Tmax = 410.1 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) Rthj-a 120 K/W 112 Rthj-pin4 = 31.7 K/W 120 K/W Zthj-a 100 Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) 100 92 90 Footprint 300 mm 2 600 mm 2 80 80 78 70 60 40 60 20 50 40 0 100 200 300 400 500 mm 2 600 A 0 -3 10 10-2 10-1 100 101 102 tp s 103 Infineon Technologies AG AG Infineon Technologies 23 23 P-DSO-16-1 4 -0.2 1.27 L 0.1 0.35 +0.15 2) 8 max. 0.35 x 45 1) 0.19 +0.06 Package e A L B P-DSO-16-1 1.27 5.69 1.31 0.65 1.75 max. 0.2 -0.1 1.45 -0.2 Footprint/Dimensions 0.4 +0.8 0.2 16x 9 1 8 B e 6 0.2 16 A Reflow soldering 10 -0.21) Index Marking PC-Board Dimensions in mm Application-Board for Rth - Measurement P-DSO-14-4 -16-1 3 Footprint only 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) Finite Element Method Footprint only; Ta = 298 K; Tmax = 419.1 K Diagrams 130 Rthj-a Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) 121 K/W Rthj-pin4 = 48.2 K/W 110 90 80 80 60 70 40 60 20 50 40 Footprint 100 100 0 100 200 300 400 500 mm 2 600 A 24 24 Zthj-a 140 K/W Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) Infineon Technologies AG Infineon Technologies AG 0 -3 10 10-2 10-1 100 101 102 tp s 103 Package and Thermal Information 0.4 +0.8 0.35 +0.15 2) L 11 B e 20 10.3 0.3 0.1 0.2 20x 8max. 1.27 9 7.6 -0.21) 0.23 +0.0 Package e A L B P-DSO-20-1 1.27 9.73 1.67 0.65 0.35 x 45 2.65 max. 0.2 -0.1 2.45 -0.2 P-DSO-20-1 Footprint/Dimensions A 1 12.8 1) 10 -0.2 Reflow soldering Dimensions in mm Index Marking Application-Board for Rth - Measurement 3 Footprint only PC-Board P-DSO-20-1 -20-6 -24-3 -28-6 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) Finite Element Method Footprint only; Ta = 298 K; Tmax = 407 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) Rthj-a 120 K/W 109 Rthj-pin5 = 43.6 K/W Zthj-a 120 K/W Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) 100 Footprint 80 90 60 80 70 40 60 20 50 40 0 100 200 300 400 500 mm 2 600 A 0 -3 10 10-2 10-1 100 101 102 tp s 103 Infineon Technologies AG AG Infineon Technologies 25 25 P-DSO-20-6 0.4 +0.8 0.35 +0.15 2) L GND 11 GND B e 20 10.3 0.3 0.1 0.2 20x 8max. 1.27 9 7.6 -0.21) 0.23 +0.0 Package e A L B P-DSO-20-6 1.27 9.73 1.67 0.65 0.35 x 45 2.65 max. 0.2 -0.1 2.45 -0.2 Footprint/Dimensions A 1 12.8 1) 10 -0.2 Reflow soldering Dimensions in mm Index Marking PC-Board Application-Boards for Rth - Measurement P-DSO-20-6 -24-3 -28-6 1 6 cm P-DSO-20-6 -24-3 -28-6 2 3 cm a 3 Footprint only 0.375 a/2 a/2 0.3 0.3 0.375 P-DSO-20-1 -20-6 -24-3 -28-6 a 1 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 17.32 mm Finite Element Method 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 12.247 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 372 K A = 300 mm; Ta = 298 K; Tmax = 379 K Footprint only; Ta = 298 K; Tmax = 397 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) Rthj-a 110 K/W 100 Rthj-pin5 = 22.9 K/W 90 Zthj-a 120 K/W Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) Footprint 300 mm 2 600 mm 2 80 81 80 74 70 40 60 20 50 40 0 100 200 300 400 500 mm 2 600 A 26 60 Infineon Technologies AG 0 -3 10 10-2 10-1 100 101 102 tp s 103 Package and Thermal Information GND 13 GND B e 24 10.3 0.3 0.1 0.2 24x 8max. 0.4 +0.8 1.27 0.35 +0.15 2) L +0.09 7.6 -0.21) 0.23 Package e A L B P-DSO-24-3 1.27 9.73 1.67 0.65 0.35 x 45 2.65 max. 0.2 -0.1 2.45 -0.2 P-DSO-24-3 Footprint/Dimensions A 1 Reflow soldering 15.6 -0.4 1) 12 Dimensions in mm Index Marking Application-Boards for Rth - Measurement P-DSO-20-6 -24-3 -28-6 1 6 cm P-DSO-20-6 -24-3 -28-6 2 3 cm a 3 Footprint only 0.375 P-DSO-20-1 -20-6 -24-3 -28-6 a/2 a/2 0.3 0.3 0.375 PC-Board a 1 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 17.32 mm 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 12.247 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 358 K A = 300 mm; Ta = 298 K; Tmax = 365 K Finite Element Method Footprint only; Ta = 298 K; Tmax = 374 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) Rthj-a 80 K/W 76.4 75 Rthj-pin6 = 20.5 K/W 70 90 K/W Zthj-a 67.4 70 Footprint 300 mm 2 600 mm 2 60 65 60.5 60 50 40 55 30 50 20 45 10 40 Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) 0 100 200 300 400 500 mm 2 600 A 0 -3 10 10-2 10-1 100 101 102 tp s 103 Infineon Technologies AG 27 P-DSO-28-6 +0.09 0.4 +0.8 GND 15 GND B e 28 10.3 0.3 0.1 0.2 28x 8max. 1.27 0.35 +0.15 2) L 7.6 -0.21) 0.23 Package e A L B P-DSO-28-6 1.27 9.73 1.67 0.65 0.35 x 45 2.65 max. 0.2 -0.1 2.45 -0.2 Footprint/Dimensions A 1 Reflow soldering 18.1 -0.4 1) 14 Dimensions in mm Index Marking PC-Board Application-Boards for Rth - Measurement P-DSO-20-6 -24-3 -28-6 1 6 cm P-DSO-20-6 -24-3 -28-6 2 3 cm a 3 Footprint only 0.375 a/2 a/2 0.3 0.3 0.375 P-DSO-20-1 -20-6 -24-3 -28-6 a 1 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 17.32 mm Finite Element Method 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 12.247 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 349 K A = 300 mm; Ta = 298 K; Tmax = 354 K Footprint only; Ta = 298 K; Tmax = 359 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) 65 K/W 61.4 Rthj-a 60 Rthj-pin7 = 20.1 K/W Zthj-a 70 K/W Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) Footprint 300 mm 2 600 mm 2 50 56 55 51 40 30 50 20 45 40 10 0 100 200 300 400 500 mm 2 600 A 28 Infineon Technologies AG 0 -3 10 10-2 10-1 100 101 102 tp s 103 Package and Thermal Information B Package e A L B P-DSO-20-10 1.27 13.48 1.83 0.68 15.74 0.1 (Heatsink) 1.27 L 0.4 +0.13 6.3 0.1 0.25 M A 20x e 1 10 GND B 11 Heatsink 0.95 0.15 14.2 0.3 0.25 M B 20 5 3 0.25 2.8 1.3 1.2 -0.3 Footprint/Dimensions +0.0 -0.027 0 +0.15 3.25 0.1 3.5 max. P-DSO-20-10 11 0.15 1) A Index Marking Reflow soldering 1 x 45 15.9 0.15 1) Dimensions in mm A Application-Boards for Rth - Measurement P-DSO-20-10 P-DSO-20-10 a P-DSO-20-10 0.375 a 3 Footprint only a/2 a/2 2 3 cm 0.3 0.3 0.375 1 6 cm PC-Board 1 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 17.32 mm 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 12.247 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 3 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 406 K A = 300 mm; Ta = 298 K; Tmax = 421 K Finite Element Method Footprint only; Ta = 298 K; Tmax = 463 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) 60 K/W 55 Rthj-a 55 Rthj-c = 2.4 K/W 50 60 K/W Zthj-a 50 Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) Footprint 300mm 2 600 mm 2 40 45 30 41 40 20 36 35 30 10 0 100 200 300 400 500 mm 2 600 A 0 -3 10 10-2 10-1 100 101 102 tp s 103 Infineon Technologies AG 29 15.74 0.1 (Heatsink) 0.65 6.3 0.1 0.25 M A 36x 36 19 1 18 Heatsink 0.95 0.15 14.2 0.3 GND 0.25 B B e 0.25 +0.13 5 3 Package e A L B P-DSO-36-10 0.65 13.48 1.83 0.45 B 0.25 1.3 1.1 0.1 L 11 0.15 1) 2.8 0 +0.1 3.25 0.1 3.5 max. Footprint/Dimensions +0.0 -0.027 P-DSO-36-10 A Index Marking Reflow soldering PC-Board 1 x 45 15.9 0.15 1) Dimensions in mm A Application-Boards for Rth - Measurement P-DSO-36-10 P-DSO-36-10 FR4; 47 x 50 x 1.5 mm; 70 Cu A = 600 mm; 24.5 x 24.5 mm Finite Element Method FR4; 47 x 50 x 1.5 mm; 70 Cu A = 300 mm; 16 x 19 mm FEM Simulation (chip area 2 mm; Pv = 3.5 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 398 K A = 300 mm; Ta = 298 K; Tmax = 427 K Diagrams Rthj-a 60 K/W Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) Rthj-c = 2 K/W 60 K/W Zthj-a 50 Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) 50 40 45 40 300 mm 2 600 mm 2 30 36.8 35 20 30 28.6 25 20 0 100 200 300 400 500 mm 2 600 A 30 30 Infineon Technologies AG Infineon Technologies AG 10 0 -3 10 10-2 10-1 100 101 102 tp s 103 Package and Thermal Information SCT595-5-1 Footprint/Dimensions 2.9 0.2 (2.2) B 1.4 1.1 max 1.2 +0.1 -0.05 (0.3) 1 0.95 0.25 M B 2 3 GND 0.3 +0.1 -0.05 10max 1.6 0.1 0.5 0.8 4 2.6 max 5 0.1 max +0.2 acc. to DIN 6784 10max 1.9 2.9 A 0.95 Reflow soldering GND 0.15 +0.1 -0.06 0.6 +0.1 -0.05 0.20 M A 1.9 Dimensions in mm Application-Boards for Rth - Measurement SCT595 1 6 cm PC-Board SCT595 2 3 cm a 0.375 SCT595 3 Footprint only a FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 17.32 mm 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 12.247 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 0.2 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 315 K I Q GND I Q INH 1 GND I Q INH 1 GND INH a/2 a/2 0.3 0.3 0.375 A = 300 mm; Ta = 298 K; Tmax = 318 K Finite Element Method Footprint only; Ta = 298 K; Tmax = 334 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) Rthj-a 200 K/W 178.7 Rthj-pin5 = 25.9 K/W 160 140 120 98.5 100 80 87 0 100 200 300 400 500 mm 2 600 A Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) 200 K/W Zthj-a 160 140 120 100 80 60 40 20 0 -3 10 Footprint 300 mm 2 600 mm 2 10-2 10-1 100 101 102 tp s 103 Infineon Technologies AG AG Infineon Technologies 31 31 SOT223-4-2 Footprint/Dimensions 1.6 0.1 6.50.2 3 0.1 B 0.1 max 3.5 0.5 min 4.8 1.2 1.1 1.4 1 2 3.5 0.2 1.4 +0.2 acc. to DIN 6784 15max GND 4 7 0.3 B 3 0.280.04 2.3 0.70.1 4.6 Reflow soldering 0.25 PC-Board M A 0.25 M Dimensions in mm B Application-Boards for Rth - Measurement SOT223 SOT223 SOT223 a/2 2 3 cm 3 Footprint only a/2 a a 1 6 cm 0.3 I 0.3 Q GND I 1 Q GND I 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 24.49 mm Finite Element Method Q GND 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 17.32 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 0.5 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 332 K A = 300 mm; Ta = 298 K; Tmax = 339 K Footprint only; Ta = 298 K; Tmax = 380 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) Rthj-a 180 K/W 164.3 Rthj-pin4 = 16.5 K/W Zthj-a 140 Footprint 300 mm 2 600 mm 2 100 80 100 60 40 81.2 80 68 0 100 200 300 400 500 mm 2 600 A 32 32 140 120 120 60 180 K/W Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) Infineon Technologies AG Infineon Technologies AG 20 0 -3 10 10-2 10-1 100 101 102 tp s 103 Package and Thermal Information P-TO252-3-1 Footprint/Dimensions 6.5 +0.15 -0.10 2.3 +0.05 -0.10 A 5.76 GND 0.51 min (4.17) 0.8 0.15 1 0.1 1 0.15 max per side 1.2 3 0...0.15 0.5 +0.08 -0.04 3x 0.75 0.1 2.28 4.57 Reflow soldering 0.9 +0.08 -0.04 B 5.4 0.1 9.9 0.5 6.22 -0.2 2.2 10.6 6.4 5.8 10.1 0.25 M 0.1 A B Dimensions in mm Application-Boards for Rth - Measurement P-TO252-3-1 P-TO252-3-1 a 1 6 cm P-TO252-3-1 3 2 3 cm a a/2 I PC-Board Footprint only a/2 Q I 1 Q I 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 24.49 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 17.32 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 353 K Q 1 A = 300 mm; Ta = 298 K; Tmax = 376 K Finite Element Method Footprint only; Ta = 298 K; Tmax = 442 K Diagrams Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) Rthj-a 160 K/W 143.9 Rthj-c = 1.8 K/W Zthj-a 160 K/W Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) 120 120 100 100 80 80 78 40 60 54.7 40 Footprint 300 mm 2 600 mm 2 60 0 100 200 300 400 500 mm 2 600 A 20 0 -3 10 10-2 10-1 100 101 102 tp s 103 Infineon Technologies AG AG Infineon Technologies 33 33 P-TO263-5-1 Footprint/Dimensions 4.4 0.1 10 0.2 1.270.1 B 0.1 0.1 A 1 GND 2.4 0.1 81) 4.6 0.05 4.7 0.5 2.7 0.3 (15) 9.25 0.2 0.6 10.8 9.4 1.1 7.9 10.3 8.5 1) 5 16.15 5x0.8 0.1 0.5 0.1 4x1.7 Reflow soldering 0.25 PC-Board M 8max. A B 0.1 B Dimensions in mm Application-Boards for Rth - Measurement P-TO263-5-1 P-TO263-5-1 a/2 2 3 cm 3 Footprint only a/2 a a 1 6 cm P-TO263-5-1 1 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 600 mm; a = 24.49 mm Finite Element Method 1 FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn A = 300 mm; a = 17.32 mm FR4; 80 x 80 x 1.5 mm; 35 Cu, 5 Sn Footprint only FEM Simulation (chip area 2 mm; Pv = 3 W; zero airflow) A = 600 mm; Ta = 298 K; Tmax = 417 K A = 300 mm; Ta = 298 K; Tmax = 455 K Footprint only; Ta = 298 K; Tmax = 533 K Diagrams 85 K/W Rthj-a 75 70 65 60 55 50 45 40 35 Thermal Resistance Junction to Ambient Rthj-a vs. PCB Heat Sink Area A (zero airflow) 78.4 Rthj-c = 1.3 K/W Zthj-a 70 60 Footprint 300 mm 2 600 mm 2 50 40 52.4 30 20 39 0 100 200 300 400 500 mm 2 600 A 34 34 90 K/W Thermal Impedance Junction to Ambient Zthj-a vs. Single Pulse Time tp (zero airflow) Infineon Technologies AG Infineon Technologies AG 10 0 -3 10 10-2 10-1 100 101 102 tp s 103 Infineon Technologies AG's sales offices worldwide - partly represented by Siemens AG A O Siemens AG Osterreich Erdberger Lande 26 A-1031 Wien T (+43) 1-17 07-3 56 11 Fax (+43) 1-17 07-5 59 73 AUS O Siemens Ltd. 885 Mountain Highway Bayswater, Victoria 3153 T (+61) 3-97 21 21 11 Fax (+61) 3-97 21 72 75 B O Siemens Electronic Components Benelux Charleroisesteenweg 116/ Chaussee de Charleroi 116 B-1060 Brussel/Bruxelles T (+32) 2-5 36 69 05 Fax (+32) 2-5 36 28 57 Email: components@siemens.nl BR O Siemens Ltda. Semiconductores Avenida Mutinga, 3800-Pirituba 05110-901 Sao Paulo-SP T (+55) 11-39 08 25 64 Fax (+55) 11-39 08 27 28 CDN O Infineon Technologies Corporation 320 March Road, Suite 604 Canada, Ontario K2K 2E2 T (+1) 6 13-5 91 63 86 Fax (+1) 6 13-5 91 63 89 CH O Siemens Schweiz AG Bauelemente Freilagerstrasse 40 CH-8047 Zurich T (+41) 1-4 95 30 65 Fax (+41) 1-4 95 50 50 D O Infineon Technologies AG Volklinger Str. 2 D-40219 Dusseldorf T (+49) 2 11-3 99 29 30 Fax (+49) 2 11-3 99 14 81 Infineon Technologies AG Werner-von-Siemens-Platz 1 D-30880 Laatzen (Hannover) T (+49) 5 11-8 77 22 22 Fax (+49) 5 11-8 77 15 20 Infineon Technologies AG Von-der-Tann-Strae 30 D-90439 Nurnberg T (+49) 9 11-6 54 76 99 Fax (+49) 9 11-6 54 76 24 Infineon Technologies AG Weissacher Strae 11 D-70499 Stuttgart T (+49) 7 11-137 33 14 Fax (+49) 7 11-137 24 48 D O Infineon Technologies AG Halbleiter Distribution Richard-Strauss-Strae 76 D-81679 Munchen T (+49) 89-92 21 40 86 Fax (+49) 89-92 21 20 71 DK O Siemens A/S Borupvang 3 DK-2750 Ballerup T (+45) 44 77-44 77 Fax (+45) 44 77-40 17 E O Siemens S.A. Dpto. Componentes Ronda de Europa, 5 E-28760 Tres Cantos-Madrid T (+34) 91-5 14 71 51 Fax (+34) 91-5 14 70 13 F O Infineon Technologies France, 39/47, Bd. Ornano F-93527 Saint-Denis CEDEX 2 T (+33) 1-49 22 31 00 Fax (+33) 1-49 22 28 01 FIN O Siemens Components Scandinavia P.O.Box 60 FIN-02601 Espoo (Helsinki) T (+3 58) 10-5 11 51 51 Fax (+3 58) 10-5 11 24 95 Email: scs@components.siemens.se GB O Infineon Technologies Siemens House Oldbury GB-Bracknell, Berkshire RG 12 8FZ T (+44) 13 44-39 66 18 Fax (+44) 13 44-39 66 32 O H Simacomp Kft. Lajos u. 103 H-1036 Budapest T (+36) 1-4 57 16 90 Fax (+36) 1-4 57 16 92 HK O Infineon Technologies Hong Kong Ltd. Suite 302, Level 3, Festival Walk, 80 Tat Chee Avenue, Yam Yat Tsuen, Kowloon Tong Hong Kong T (+8 52) 28 32 05 00 Fax (+8 52) 28 27 97 62 O I Siemens S.p.A. Semiconductor Sales Via Piero e Alberto Pirelli, 10 I-20126 Milano T (+39) 02-66 76 -1 Fax (+39) 02-66 76 43 95 Internet-address: http://www.infineon.com IND O NL O Siemens Ltd. Components Division No. 84 Keonics Electronic City Hosur Road Bangalore 561 229 T (+91) 80-8 52 11 22 Fax (+91) 80-8 52 11 80 Siemens Electronic Components Benelux Postbus 16068 NL-2500 BB Den Haag T (+31) 70-3 33 20 65 Fax (+31) 70-3 33 28 15 Email: components@siemens.nl Siemens Ltd. CMP Div, 5th Floor 4A Ring Road, IP Estate New Delhi 110 002 T (+91) 11-3 31 99 12 Fax (+91) 11-3 31 96 04 NZ O Siemens Ltd. CMP Div, 4th Floor 130, Pandurang Budhkar Marg, Worli Mumbai 400 018 T (+91) 22-4 96 21 99 Fax (+91) 22-4 96 22 01 IRL O Siemens Ltd. Electronic Components Division 8, Raglan Road IRL-Dublin 4 T (+3 53) 1-2 16 23 42 Fax (+3 53) 1-2 16 23 49 O IL Nisko Ltd. 2A,Habarzel St. P.O. Box 58151 61580 Tel Aviv - Isreal T (+9 72) 3-7 65 73 00 Fax (+9 72) 3-7 65 73 33 J O Siemens Components K.K. Talanawa Park Tower 12F & 17F 3-20-14, Higashi-Gotanda, Shinagawa-ku Tokyo T (+81) 3-54 49 64 11 Fax (+81) 3-54 49 64 01 MAL O Infineon Technologies AG Sdn Bhd Bayan Lepas Free Industrial Zone 1 11900 Penang T (+60) 4-6 44 99 75 Fax (+60) 4-6 41 48 72 N O Siemens Components Scandinavia Ostre Aker vei 24 Postboks 10, Veitvet N-0518 Oslo T (+47) 22-63 30 00 Fax (+47) 22-68 49 13 Email: scs@components.siemens.se Siemens Auckland 300 Great South Road Greenland Auckland T (+64) 9-5 20 30 33 Fax (+64) 9-5 20 15 56 P O Siemens S.A. an Componentes Electronicos R. Irmaos Siemens, 1 Alfragide P-2720-093 Amadora T (+351) 1-4 17 85 90 Fax (+351) 1-4 17 80 83 PK O Siemens Pakistan Engineering Co.Ltd. PO Box 1129, Islamabad 44000 23 West Jinnah Ave Islamabad T (+92) 51-21 22 00 Fax (+92) 51-21 16 10 PL O Siemens SP. z.o.o. ul. Zupnicza 11 PL-03-821 Warszawa T (+48) 22-8 70 91 50 Fax (+48) 22-8 70 91 59 ROK O Siemens Ltd. Asia Tower, 10th Floor 726 Yeoksam-dong, Kang-nam Ku CPO Box 3001 Seoul 135-080 T (+82) 2-5 27 77 00 Fax (+82) 2-5 27 77 79 RUS O INTECH electronics ul. Smolnaya, 24/1203 RUS-125 445 Moskva T (+7) 0 95-4 51 97 37 Fax (+7) 0 95-4 51 86 08 O S Siemens Components Scandinavia Osterogatan 1, Box 46 S-16493 Kista T (+46) 8-7 03 35 00 Fax (+46) 8-7 03 35 01 Email: scs@components.siemens.se RC O Infineon Technologies Asia Pacific Pte. Ltd. Taiwan Branch 10F, No. 136 Nan King East Road Section 23, Taipei T (+8 86) 2-27 73 66 06 Fax (+8 86) 2-27 71 20 76 SGP O Infineon Technologies Asia Pacific, Pte. Ltd. 168 Kallang Way Singapore 349 253 T (+65) 8 40 06 10 Fax (+65) 7 42 62 39 USA O Infineon Technologies Corporation 1730 North First Street San Jose, CA 95112 T (+1) 4 08-5 01 60 00 Fax (+1) 4 08-5 01 24 24 Siemens Components, Inc. Optoelectronics Division 19000 Homestead Road Cupertino, CA 95014 T (+1) 4 08-2 57 79 10 Fax (+1) 4 08-7 25 34 39 Siemens Components, Inc. Special Products Division 186 Wood Avenue South Iselin, NJ 08830-2770 T (+1) 7 32-9 06 43 00 Fax (+1) 7 32-6 32 28 30 VRC O Infineon Technologies Hong Kong Ltd. Beijing Office Room 2106, Building A Vantone New World Plaza No. 2 Fu Cheng Men Wai Da Jie 100037 Beijing T (+86) 10-68 57 90 -06, -07 Fax (+86) 10-68 57 90 08 Infineon Technologies Hong Kong Ltd. Chengdu Office Room 14J1, Jinyang Mansion 58 Tidu Street Chengdu, Sichuan Province 610 016 T (+86) 28-6 61 54 46 / 79 51 Fax (+86) 28-6 61 01 59 Infineon Technologies Hong Kong Ltd. Shanghai Office Room 1101, Lucky Target Square No. 500 Chengdu Road North Shanghai 200003 T (+86) 21-63 61 26 18/19 Fax (+86) 21-63 61 11 67 Infineon Technologies Hong Kong Ltd. Shenzhen Office Room 1502, Block A Tian An International Building Renim South Road Shenzhen 518 005 T (+86) 7 55-2 28 91 04 Fax (+86) 7 55-2 28 02 17 ZA O Siemens Ltd. Components Division P.O.B. 3438 Halfway House 1685 T (+27) 11-6 52 -27 02 Fax (+27) 11-6 52 20 42 06.10.99 To t a l Q u a l i t y M a n a g e m e n t Qualitat hat fur uns eine umfassende Bedeutung. Wir wollen allen Ihren Anspruchen in der bestmoglichen Weise gerecht werden. Es geht uns also nicht nur um die Produktqualitat - unsere Anstrengungen gelten gleichermaen der Lieferqualitat und Logistik, dem Service und Support sowie allen sonstigen Beratungs- und Betreuungsleistungen. Dazu gehort eine bestimmte Geisteshaltung unserer Mitarbeiter. Total Quality im Denken und Handeln gegenuber Kollegen, Lieferanten und Ihnen, unserem Kunden. Unsere Leitlinie ist, jede Aufgabe mit Null Fehlern" zu losen - in offener Sichtweise auch uber den eigenen Arbeitsplatz hinaus - und uns standig zu verbessern. Unternehmensweit orientieren wir uns dabei auch an top" (Time Optimized Processes), um Ihnen durch groere Schnelligkeit den entscheidenden Wettbewerbsvorsprung zu verschaffen. Geben Sie uns die Chance, hohe Leistung durch umfassende Qualitat zu beweisen. Quality takes on an allencompassing significance at Semiconductor Group. For us it means living up to each and every one of your demands in the best possible way. So we are not only concerned with product quality. We direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. Part of this is the very special attitude of our staff. Total Quality in thought and deed, towards co-workers, suppliers and you, our customer. Our guideline is "do everything with zero defects", in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. Throughout the corporation we also think in terms of Time Optimized Processes (top), greater speed on our part to give you that decisive competitive edge. Give us the chance to prove the best of performance through the best of quality - you will be convinced. Wir werden Sie uberzeugen. Published by Infineon Technologies AG Ordering No. B112-H7482-G1-X-7600 Printed in Germany TB 01005. NB